Sr Principal Design Engineer
Cadence · Bangalore, India
Open. First seen 2 October 2026.
Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 12-14 yrs of work experiences in VLSI domain with Master's/bachelor's degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology…
Read the full posting on www.themuse.com
Posting history
Reposted once since 20 September 2026: a posting for this role in Bangalore, India was taken down and the role was posted again.
- 2 October 2026 – open (this posting)
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 20 September 2026 – closed 29 September 2026
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