SI/PI Engineer

Job Summary

We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs — from early architecture through final release — ensuring electrical margins are met across interfaces running at multi-gigabit data rates.

Key Responsibilities

• Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet.
• Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers.
• Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements.
• Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation.
• Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave.
• Collaborate with PCB design and layout engineers, and ASIC teams to define and review design guidelines early in the product lifecycle.
• Support bring-up, debug signal quality issues, and document root-cause findings with clear corrective actions.
• Develop and maintain simulation-to-hardware correlation databases to continuously improve modelling accuracy.

You may be a good fit if you have (Must-have qualifications)

• B.S. or M.S. in Electrical Engineering or a closely related discipline.
• 5+ years of hands-on SI/PI experience on high-speed designs (>1 Gbps serial links or DDR4/5 and HBM3/4 memory interfaces).
• Proficiency with industry SI/PI EDA tools (Cadence Sigrity, Ansys SIwave/HFSS, Keysight ADS, or equivalent).
• Strong understanding of transmission line theory, return-loss, insertion-loss, crosstalk, eye-diagram analysis, and jitter decomposition.
• Experience with PDN modelling, target impedance methodology, and DC IR analysis.
• Working knowledge of multi-layer PCB stack-up design and controlled-impedance trace routing.
• Hands-on lab skills: S-parameter measurements with VNA, time-domain reflectometry (TDR), BERT operation, and oscilloscope probing techniques

Strong candidates may also have experience with (Nice-to-have qualifications)

• Prior work in data center, AI/ML accelerator, networking, or high-performance computing (HPC) hardware environments.
• Experience scripting automated SI/PI simulation flows using Python or MATLAB to reduce manual simulation turnaround time.

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2,500 per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office
• Unlimited compute budget subject to ROI justification

How we’re different

We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.