CODEC Video Compression Engineer/Developer
- Salary
- $161,500 - $226,000
- Level
- Mid
Not stated in the posting: work type, visa.
Open. First seen 2 October 2026.
About the role
Neros Technologies's standard text
Who we are
Neros is a defense technology company rebuilding America’s drone industrial base. We design and manufacture high-performance unmanned systems that are tested in combat, iterated at startup speed, and built at massive scale. Our team culture is fast, hands-on, and obsessed with closing the gap between design and deployment.
As drones transform the character of warfare, Neros is delivering the systems the West needs to compete on the modern battlefield and deter the adversaries of democracy. We’re hiring engineers, operators, and builders who want to move fast, take on extreme ownership, and get capability into the hands of warfighters in months, not years.
What you will be doing
We are seeking a highly skilled CODEC Video Compression Engineer/Developer to build low cost FPV digital video, similar to DJI 04.
They will design, optimize, and implement low-latency advanced video compression algorithms while maintaining high visual quality, for real time video streaming application. You will work closely with cross-functional teams to deliver high-quality, low-latency wireless video. This role blends deep knowledge of video processing, mathematics, and software/hardware optimization to enable video transmission with minimum latency and reduced bandwidth usage.
Responsibilities
- Design and implementation of dual CPU/GPU hybrid video compression encoder architecture that can seamlessly combine SW and HW encoding engines
- Design, develop, and optimize video compression algorithms in C/C++, Assembly, Rust or similar languages
- Implement and optimize encoder/decoder pipelines for real-time applications
- Analyze and improve codec performance for speed, quality, and efficiency across CPU, GPU
- Perform error handling
- Conduct performance benchmarking, debugging, and quality assurance testing: Develop and use objective and subjective metrics to evaluate codec performance
- Collaborate with hardware and software teams to integrate CODEC solutions into products, using high-level synthesis, or FPGA/ASIC design flows
- Stay updated on emerging video standards, compression techniques, and industry trends
You should have the following
- Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field
- Solid understanding of video compression theory, motion estimation, transform coding, MC DCT, VBSMC, entropy coding, and rate control
- Codec implementation experience in developing actual software and hardware that encodes and decodes video data according to a specific compression format
- System Verilog experience (HLS/C++)
- Solid understanding of video compression standards (H.264, H.265/HEVC, H.266, VP9, AV1) and rate control algorithms
- Experience with hardware implementations using dedicated chips (FPGAs, ASICs, DSPs), and hybrid implementations using software for control logic with hardware accelerators GPUs (NVENC, NVDEC). Experience with GPU acceleration (CUDA, Vulkan, OpenCL)
- Strong proficiency in C/C++ and experience with SIMD optimizations (SSE, AVX, NEON)
- Front-end development for ****control of performance-critical code
- Experience with multithreaded programming and performance profiling tools, debugging, and performance optimization
- Excellent problem-solving skills and ability to work in a collaborative environment
Nice to have
- Backend development (FFmpeg framework, GStreamer)
- Knowledge of container formats (MP4, MKV, MPEG-TS)
- Experience with ML–based video enhancement or compression
US Salary Range
$161,500 - $226,000 USD
The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are considered part of Neros' total compensation package.
Neros Technologies's standard text
We’re an equal opportunity employer. We welcome all applicants without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
What this role asks for
76% of this description is written for the role. The rest is Neros Technologies's standard text, folded away below.
Read against Neros Technologies's other open postings on this site.
The team: RF Engineering HIRES STEADILY
This role is one of 7 open in RF Engineering. 4 were posted in the last 30 days and the oldest in February: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Embedded Systems (4 of 7), Python (4 of 7), MATLAB (3 of 7), Test Automation (3 of 7), C (2 of 7), FPGA (2 of 7), Verilog (2 of 7)
OTHER ROLES ON THIS TEAM
- Senior Wireless Engineer posted Oct 13
- RF Test Technician posted Oct 8
- Principal Connectivity Engineer posted Oct 1
- Senior EW Test & Evaluation Engineer posted Oct 1
- Lead RF Test & Integration Engineer posted Aug 31
- Senior RF Engineer (Hardware) posted Aug 25
From the team and dates on Neros Technologies's own job board.
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