Mixed-signal Verification Engineer
- Level
- Mid
- Work type
- On-site · Paris
Not stated in the posting: salary, visa.
Open. First seen 2 October 2026.
About the role
Meet Arago and the Aragonians
Arago’s mission is to re-engineer the foundations of computing from first principles.
The explosive growth of AI is pushing the industry to rethink how processors are built. Arago is meeting that challenge with a proprietary technology that fuses optical and CMOS technologies to deliver an order-of-magnitude increase in performance.
Arago is the fastest, and currently the only, company to have built such a processor. It's backed by leading deep-tech investors and some of the most respected figures in semiconductors and computing, including the CEO of Arm, the founder of macOS who worked directly with Steve Jobs at Apple, an Nvidia Fellow, the Head of Optics at Google, and many other industry leaders.
Our work is guided by three clear values: do great things, move with high velocity, and operate as one unit. We work in a demanding environment where constant learning, ownership, and execution are expected, and where exceptional people have the opportunity to do their life’s work.
What you’ll do
As Mixed-Signal Verification Engineer you will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on-Chip, working across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.
Required Skills and Experience
- Strong hands-on experience in ASIC or SoC verification.
- Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces.
- Experience with AMS (analog-mixed-signal) co-simulation flow, and setting up mixed-signal testbenches.
- Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology.
- Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage.
- Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts.
- Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior.
- Experience with scripting and automation, preferably Python, Tcl, shell, or similar.
- Language: English at a proficient level.
Responsibilities
- Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs.
- Build and maintain verification environments at block, subsystem, and SoC level.
- Develop tests, assertions, checkers, scoreboards, and functional coverage.
- Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions.
- Run regressions, analyze coverage, debug failures, and drive verification to sign-off.
- Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation.
- Work closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues.
Nice to have
- Verification experience with complex high-speed interface IP such as PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL, or similar PHY-based interfaces.
- Experience verifying interface initialization, link training, calibration, adaptation, clocking, power-state transitions, or other digital/analog control loops.
- Experience with real-number modeling, SystemVerilog RNM, wreal, Verilog-AMS, or equivalent mixed-signal verification techniques.
- Experience developing or integrating behavioral models of analog/PHY components into digital verification environments.
- Experience with SoC-level integration and verification of complex interface IP.
- Experience with low-power verification, power-state management, or UPF.
- Experience driving a complex IP or SoC verification effort through coverage closure and tape-out.
Pay and benefits
- Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions.
- Meaningful stock option plan offered (included in the majority of full time offers).
- Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays.
- Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.
We look forward to hearing how you can help shape the future of AI at Arago.
What this role asks for
Particular to this role
Embedded Systems
Rare in Arago's other 13 open postings.
Standard for software engineering roles
Python
Common in software engineering postings at any company.
Compared with Arago's other open jobs.
The team: Digital IC HIRES STEADILY
This role is one of 5 open in Digital IC. 1 was posted in the last 30 days and the oldest in May: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Hugging Face (3 of 5), Machine Learning (3 of 5), Verilog (3 of 5), FPGA (2 of 5), Python (2 of 5)
OTHER ROLES ON THIS TEAM
- Senior Hardware Design Engineer posted Oct 13
- Architecture Modeling Engineer posted Aug 28
- Digital Verification Engineer posted Jul 25
- Physical Design Engineer posted May 16
From the team and dates on Arago's own job board.
Similar jobs
- Mixed-Signal IC Design Engineer at Apple
Shares 3 skills: Verilog, Embedded Systems, Python - Senior Analog / Mixed-Signal IC Design Engineer at Ethernovia, Inc.
Shares 3 skills: Verilog, Embedded Systems, Python - FPGA Engineer at ALTEN Technology USA
Shares 3 skills: Verilog, Embedded Systems, Python · same seniority - FPGA Design and Verification Engineer at ASML
Shares 3 skills: Verilog, Embedded Systems, Python · same seniority - FPGA Design & Verification Engineer-US Only at A2e Technologies
Shares 3 skills: Verilog, Embedded Systems, Python · same seniority - Technical Sourcer at Arago
Also at this company
Is this your posting? Email info@careerholo.com to have it removed.