Kernel Engineer (Custom Silicon), Hardware
- Salary
- $200,000 - $420,000
- Level
- Senior
- Visa
- Sponsors visas
Not stated in the posting: work type.
Open. First seen 3 October 2026.
About the role
At River, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, custom training infrastructure, next-generation UIs, and frontier deep learning research.
River AI Inc.'s standard text
Who we are
We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.
About the Role
We are looking for exceptional performance and kernel generation engineers to build the foundational compute engine for our high-performance custom silicon. In this role, you will design and implement robust kernel generators that programmatically emit optimized low-level assembly code for our greenfield hardware architecture.
You will bridge the gap between high-level compilation and raw hardware capability, pushing our custom architecture to its absolute theoretical limits for critical deep learning operations (including GEMMs, FlashAttention, and custom activations). You will collaborate closely up and down the stack with compiler engineers, silicon architects, and deep learning researchers to unlock maximum compute efficiency.
What You’ll Do
- Kernel Generator Development: Design and build C++ code-generation frameworks and meta-programming toolchains that automatically emit optimized custom ISA assembly code.
- Low-Level Compute Optimization: Author and optimize core deep learning primitives (GEMM/MatMul, Attention mechanisms, Convolutions, and element-wise layers) directly targeted at our custom hardware.
- Microarchitectural Tuning: Hand-craft and automate instruction scheduling, register allocation, and software pipelining to maximize ALU utilization and hide execution latency on our silicon.
- Memory Hierarchy Management: Design sophisticated tiling, double-buffering, and data-movement strategies to optimize on-chip SRAM utilization and minimize memory bandwidth bottlenecks.
- HW/SW Co-Design: Partner with the RTL and architecture teams to evaluate hardware simulations, provide feedback on the ISA, and influence the design of future compute units based on kernel execution profiles.
- Performance Profiling & Validation: Benchmark generated assembly against hardware simulators and silicon, utilizing hardware performance counters to eliminate performance gaps and ensure mathematical correctness.
Minimum Qualifications:
- Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field, and 5+ years of practical industry experience in low-level performance programming.
- Deep understanding of hardware programming models (e.g., CUDA, Triton, CUTLASS, or custom accelerator assembly) and a proven track record of shipping highly optimized kernels.
- Advanced knowledge of Computer Architecture, including vector units, execution pipelines, register files, and complex memory hierarchies (caches, SRAM, HBM/DRAM).
- Proficiency in modern C++ for building robust, scalable meta-programming and code-generation frameworks.
- Strong mathematical foundation in linear algebra operations and deep learning primitives.
- A highly collaborative mindset to push boundaries and co-design effectively with hardware and compiler teams.
River AI Inc.'s standard text
Preferred Qualifications: (We encourage you to apply even if you don't meet all of these)
- Deep familiarity with implementing microarchitectural optimizations for Tensor Cores, matrix multiply-accumulate units, or custom vector extensions.
- Experience utilizing advanced C++ template metaprogramming or code-generation techniques to automate the creation of heavily parameterized kernel variants.
- Advanced experience with low-level hardware profiling tools, execution tracing, and utilizing performance counters to identify cache misses, pipeline stalls, and ALU bubbles.
Logistics
- Location: This role is based in Austin, Texas or Palo Alto, California.
- Compensation: Depending on background, skills, experience, and location, the expected annual salary range for this position is $200,000 - $420,000 USD, plus equity.
- Visa Sponsorship: We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
- Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.
What this role asks for
Standard for embedded / hardware roles
C++
Common in embedded / hardware postings at any company.
In most of River AI Inc.'s ads
Deep Learning
Named in most of its open postings, whatever the role.
90% of this description is written for the role. The rest is River AI Inc.'s standard text, folded away below.
Read against River AI Inc.'s other open postings on this site.
The team: Personal AI Hardware HIRES STEADILY
This role is one of 7 open in Personal AI Hardware. 1 was posted in the last 30 days and the oldest in May: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Deep Learning (7 of 7), C++ (5 of 7), C (4 of 7), Python (4 of 7), CUDA (3 of 7), Embedded Systems (3 of 7), Verilog (3 of 7)
OTHER ROLES ON THIS TEAM
- Design Verification Emulation, Hardware posted Sep 28
- Compiler Engineer, Hardware posted May 15
- Performance Engineer, Hardware posted May 15
- Physical Design Engineer, Hardware posted May 15
- Design Verification Engineer, Hardware posted May 15
- RTL Design Engineer, Hardware posted May 15
From the team and dates on River AI Inc.'s own job board.
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