FPGA Engineer

We’re seeking engineers who thrive on solving hard problems and turning bold ideas into real-world solutions. If you’re driven to design, develop, and test technology that truly makes an impact, you’ll feel at home here.

Quest Defense Systems and Solutions is actively hiring FPGA Engineers to design and verify digital logic solutions for major FPGA platforms including Xilinx, Altera, and Microsemi. Work spans the full development lifecycle — requirements definition, architecture, VHDL coding, simulation, integration, debug, documentation, and support through production. Applications include gigabit serial interfaces, RF/EO DSP, controls, embedded processing, and processor interfaces. Engineers collaborate with circuit card designers and systems engineers through every stage of development.

We are hiring FPGA Engineers at various levels!

Location: Onsite Tucson, AZ. Relocation assistance is available

Citizenship: Due to the nature of the work, US Citizenship is required.

Clearance: Active DoD Security Clearance

What you will be doing:

• Architect FPGA‑based systems, determining interfaces, device selection, and concept of operations (CONOPS).
• Translate system‑level requirements into FPGA requirements.
• Design and code FPGA implementations in VHDL with emphasis on reliability and maintainability.
• Perform simulation, place‑and‑route, and verification using both directed tests and constrained‑random techniques.
• Track functional and code coverage during verification.
• Integrate and debug designs in lab environments.
• Deliver production‑quality FPGA releases from prototype through full production.
• Create detailed documentation: requirements, verification plans, user guides.
• Support internal and external technical reviews.

Qualifications You Must Have:

FPGA Engineer – Mid‑Level

• Minimum 5 years’ experience including at least one of:
• Digital design & VHDL coding
• Xilinx or Microsemi device/tools experience
• Delivering FPGA solutions to system‑level applications
• Hands‑on integration & debug

FPGA Engineer – Senior/Principal Level

• Minimum 8 years of experience including at least one of the above areas.
• Ability to support complex design efforts from concept through production.
• Experience of collaborating with multidisciplinary engineering teams.

Preferred Qualifications:

• Experience in radar or image processing (RF/EO).
• Embedded systems design using ARM, Microblaze, or Nios processors.
• Experience with gigabit serial interfaces and multi‑gigabit transceivers (MGTs).
• UVM/System Verilog‑based constrained‑random verification.
• Verification using emulation platforms such as Veloce.

What You’ll Find Here

• Work That Matters – Next-generation, safety- and mission-critical projects where your contributions have real-world impact.
• Growth That’s Supported – Competitive compensation, employer-matched 401(k), certification assistance, and clear opportunities for advancement.
• A Culture That Works – A flexible, collaborative, and people-first environment where teamwork, innovation, and balance are valued.

Benefits Include

• Competitive pay, comprehensive medical/dental/life and disability coverage, 401(k) with employer match, professional development support, and a flexible, friendly workplace.

Full compensation package is based on candidate experience and certifications

Pay Ranges

$145,000—$185,000 USD

With over 25 years of aerospace and defense engineering expertise, our commitment to delivering high-quality, transformative solutions sets us apart — not just as an industry leader, but as a driving force for impactful change. Together, we’re not just leading the industry — we’re revolutionizing it.

This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation and training.The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.