Platform Validation Lead / Manager
- Level
- Lead
- Work type
- Hybrid · Hyderabad
Not stated in the posting: salary, visa.
Open. First seen 22 October 2026.
About the role
Kandou AI's standard text
At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
We are looking for a Platform Validation Lead/Manager
Location: Hyderabad, India
Responsabilities
- Own the Hyderabad platform-validation strategy for Ethernet Retimers, converting product, silicon, firmware and standards requirements into traceable test plans, entry and exit criteria, sample coverage and release decisions.
- Lead pre-silicon and post-silicon validation using simulation, FPGA or emulation and hardware-in-loop environments; drive first-silicon bring-up through power, clocks, boot, register access and module enumeration.
- Validate server and switch host integration, CMIS module-management state machines, I2C/SMBus and SPI mailbox flows, hot-plug, power sequencing, telemetry, diagnostics and fault recovery.
- Build automated regression, conformance and release-readiness workflows with requirements-to-test traceability, reproducible configurations, a known-failure catalog and evidence-based defect disposition.
- Lead and mentor the Hyderabad validation team; establish benches, equipment and lab processes, plan capacity, review results and remain hands-on in system-level debug and root-cause isolation.
- Partner across Hyderabad, Lausanne and Taiwan with SoC, DV, firmware, characterization, interoperability, product and field teams to correlate results and deliver qualified customer-ready releases.
Essential Experience
· 10+ years of silicon, system or platform validation experience on shipping SoCs, networking silicon, SerDes, retimers, PHYs, AEC/AOC or optical-module products.
· Direct ownership of at least one pre-silicon-to-post-silicon validation cycle, including first-silicon or board bring-up, qualification and release-readiness decisions.
· Hands-on system debug across silicon, boards, firmware, drivers and host applications, using JTAG, register traces, oscilloscopes, BERTs and related lab tools.
· Strong validation automation skills in Python and working C and/or C++ knowledge; experience with hardware-in-loop frameworks, CI, version control and reproducible test environments.
· Experience validating management and sideband interfaces such as CMIS, I2C//I3CSMBus, SPI, MDIO or MCTP, including state transitions, error paths, hot-plug and recovery behavior.
· Demonstrated requirements-traceable validation discipline: verification methods, pass/fail criteria, sample plans, environmental conditions, guard bands and clear evidence packages.
· Proven technical and people leadership, including hiring or mentoring engineers, managing lab priorities and driving cross-functional defect closure under a fixed schedule.
Excellent written and verbal communication; BS in Electrical Engineering, Computer Engineering or Computer Science, or equivalent experience. Ability to travel for bring-up and partner qualification windows.
Useful Experience
· Validation of 100G/lane or 200G/lane Ethernet, PAM4 SerDes, retimers, PHYs, AEC/AOC or optical modules.
· IEEE 802.3, OIF-CEI, CMIS 5.x, OSFP MSA or related electrical and module-management conformance.
· BER and FEC validation, link training and equalization, loopback test, eye and margin analysis, and correlation with characterization data.
· Secure boot, authenticated firmware update, image signing, rollback and recovery-path validation.
· Hyperscaler or tier-one OEM qualification, NIC or switch-ASIC interoperability, plugfests and customer escalation support.
· ATE or manufacturing-test correlation, EIA-364 or JEDEC qualification exposure, thermal and power validation, and multi-site program leadership.
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would love to hear from you. Together We Kandou It!!
What this role asks for
Particular to this role
FPGA
Rare in Kandou AI's other 33 open postings.
86% of this description is written for the role. The rest is Kandou AI's standard text, folded away below.
Compared with Kandou AI's other open jobs.
The team: Engineering HIRES STEADILY
This role is one of 15 open in Engineering. 5 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (11 of 15), C (8 of 15), C++ (7 of 15), Embedded Systems (7 of 15), RTOS (5 of 15), CMake (3 of 15), FPGA (3 of 15)
OTHER ROLES ON THIS TEAM
- Customer Platform, SDK & Interoperability Architect - Randa 1.6T AEC Platform posted Oct 12
- Embedded Software Technical Lead posted Oct 12
- Firmware Lead posted Oct 12
- Software Architect posted Sep 24
- System Firmware Lead (AI Memory Fabrics) – CXL/PCIe Memory fabric controller posted Sep 11
- Internship - AI Engineer posted Sep 9
- Board Product Project Control Coordinator (PCC/ PJE) posted Sep 9
- Analog Layout Engineer (Lead) posted Sep 7
- Internship - Semiconductor Engineering posted Sep 1
- Physical Design Engineers - 2 openings posted Aug 19
- Firmware Engineer Bare Metal posted Aug 19
- Firmware Architect posted Aug 19
- Digital Design Engineers - 7 openings posted Aug 19
- Digital Design Engineer, UK, CH posted Aug 19
From the team and dates on Kandou AI's own job board.
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