Memory Designer

The team: ASICS Engineering

This role is one of 67 open in ASICS Engineering. 38 were posted in the last 30 days, including 2 lead roles: the team is hiring the people who run it too.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Python (32 of 67), Verilog (24 of 67), C (20 of 67), Perl (19 of 67), C++ (18 of 67), Embedded Systems (12 of 67), FPGA (9 of 67)

OTHER ROLES ON THIS TEAM

• Tech IP Library Characterization Engineer posted Oct 8
• Physical Design Engineer, Sr. Staff posted Oct 8
• Staff Emulation Build Quality, Performance & Debug Engineer posted Oct 8
• Emulation Performance Methodology & Debug Engineer posted Oct 8
• Senior Emulation Performance Methodology & Debug Engineer posted Oct 8
• ASICS Design Verification Engineer (Vancouver, Markham OR Remote) posted Oct 8
• Next Gen, High-Speed, Memory and Cache Controller Design Engineer posted Oct 7
• Firmware Engineer, Edge AI Silicon Validation (Embedded C) posted Oct 7
• Front-End Implementation Engineer (Staff) (Timing & Synthesis)- Cork, Ireland posted Oct 7
• ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham posted Oct 7
• Design Engineer - Hod Hasharon posted Oct 7
• SOC Design Verification Engineer posted Oct 7
• Director , Engineering (GPU Physical Design) posted Oct 7
• Hardware Verification, Engineer at Qualcomm Interconnect Technology Center (QITC) - France posted Oct 7
• Next-Gen System Cache ASIC Digital Design Engineer posted Oct 7
• EDA/CAD Software Engineer, Staff posted Oct 7
• Memory Circuit Design Engineer posted Oct 7
• BEOL Process Integration Engineer, up to Sr. Staff posted Oct 6
• SOC Design Verification Engineer posted Oct 6
• SOC Debug Engineer posted Oct 6
• PMIC Design Verification Lead (Sr Staff Engineer) posted Oct 6
• Silicon Validation Senior Engineer posted Oct 6
• High-Bandwidth Memory (HBM) System Validation Lead (AI Accelerator Platform) posted Oct 6
• SOC Design Verification Staff Engineer posted Oct 5
• Camera Frontend Implementation Engineer posted Oct 5
• Architecture/System Validation Engineer posted Oct 2
• Physical Design (Multiple levels) posted Oct 2
• Systems Engineer (ML and DSP) - Cork, Ireland posted Oct 2
• SOC Design Verification Engineer posted Oct 2
• Physical Design Engineer posted Oct 2
• VLSI Frontend CAD Applications Engineer posted Oct 2
• DFT-Staff Engineer posted Oct 2
• Foundry Engineer for Advanced Technology (Device/Process/ Product) posted Oct 2
• Staff Analog IC Design Engineer (ADC) posted Oct 1
• Staff RF Hardware Engineer - Device Technology posted Oct 1
• Physical Design Engineer, Staff - Hod Hasharon posted Oct 1
• Design Verification Engineer - NPU- Engineer to Sr. Staff Engineer posted Oct 1
• SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team posted Oct 1
• Analog / Mixed-Signal IP DDR Design Senior Engineer - Cork, Ireland posted Sep 24
• Physical Design Engineer, Staff posted Sep 24
• Senior Staff Hardware Engineer - Hod Hasharon posted Sep 24
• SOC Power Architect posted Sep 23
• Microprocessor Silicon Validation and Optimization Engineer-Staff posted Sep 17
• RTL Feasibility Engineer, AI/ML Processors posted Sep 17
• SOC Design Verification Engineer-Staff posted Sep 17
• Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels) posted Sep 17
• Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels) posted Sep 17
• Senior Director SoC Architecture - AI Accelerators (Multiple Locations) posted Sep 17
• Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer posted Sep 17
• 3D Memory Chip Architect and Design, Principal Engineer posted Sep 17
• FPGA Firmware Engineer / FPGA Design Engineer posted Sep 17
• Staff ASIC Verification Engineer, Low Power AI posted Sep 17
• SOC Design Engineer posted Sep 17
• Verification Hardware Engineer posted Sep 17
• FPGA Firmware Engineer / FPGA Design Engineer posted Sep 17
• ASICS Design Verification Engineer-Senior posted Sep 17
• Connectivity Project Engineer, Principal posted Sep 17
• Connectivity Project Engineer, Principal posted Sep 17
• Physical Design Engineer- senior posted Sep 17
• ASIC DTCO, Timing and Technology Engineer posted Sep 17
• Principal Ethernet Scale-Out Architect, AI Data Center posted Sep 17
• Sr. Staff/Principal PCIE Subsystem Architect posted Sep 17
• SOC Design Verification Engineer-Staff posted Sep 17
• SOC Design Verification Engineer posted Sep 17
• Staff Engineer, Physical Design/Implementation posted Sep 17
• Engineer posted Sep 17
• Digital Design Verification Engineer, Staff posted Sep 17

From the team and dates on Qualcomm's own job board.