Failure Analysis Engineer - Nanoprobing

The team: Hardware Engineering

This role is one of 27 open in Hardware Engineering. 10 were posted in the last 30 days.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

FPGA (14 of 27), Python (11 of 27), Verilog (11 of 27), Perl (10 of 27), C (7 of 27), C++ (7 of 27), Embedded Systems (6 of 27)

OTHER ROLES ON THIS TEAM

• RTL Design Engineer - Security /Staff posted Oct 8
• NPU Design implementation (Synthesis) Principal/Manager posted Oct 7
• PMIC Design Verification Sr Engineer posted Oct 7
• CPU Core Validation Engineer (Staff/Senior Staff) - CPU Pipeline and uarch experts posted Oct 7
• Memory Circuit Designer posted Oct 7
• Sr. Director, AI Technology & Manufacturing posted Oct 7
• GPU (RTL) Design - Sr Engineer posted Oct 6
• MBIST Diagnostics Engineer - Sr Staff/Staff Engineer posted Oct 5
• Hardware Design Engineer - Sr Staff (Austin OR San Diego) posted Oct 1
• Sr Hardware Design Engineer posted Oct 1
• Senior Hardware Engineer, Power Delivery (AI Data Center) posted Sep 24
• PostSi Debug Validation Engineer posted Sep 24
• FPGA prototyping/FPGA design Engineer (Lead/Staff) posted Sep 23
• SoC STA/Timing Engineer (Senior Staff/Principal) posted Sep 23
• Staff Quality Engineer, Customer Quality posted Sep 17
• DFT Engineer (Senior to Staff level) posted Sep 17
• DFT Engineer, Principal posted Sep 17
• Synthesis Engineer, Sr Lead posted Sep 17
• Sr. Product and Test Engineer posted Sep 17
• PMIC Design Engineer, Staff posted Sep 17
• PMIC Design Engineer, Sr Staff posted Sep 17
• PMIC Design Engineer, Senior posted Sep 17
• RISCV CPU Design Verification Staff Engineer posted Sep 17
• RISCV CPU Design Verification Principal Manager/ Engineer posted Sep 17
• RISCV CPU Design Verification Staff Engineer posted Sep 17
• Synthesis Engineer posted Sep 17

From the team and dates on Qualcomm's own job board.