NPU Architect Engineer, Multimedia Lab
San Jose, CA
- Salary
- $162000 - $316800 annually
- Level
- Lead
Not stated in the posting: work type, visa.
Open. First seen 1 November 2026.
About the role
Responsibilities Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for…
What this role asks for
Particular to this role
Embedded Systems · FPGA
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