Microarchitect and RTL Design Engineer
- Level
- Senior
Not stated in the posting: salary, work type, visa.
Open. First seen 3 October 2026.
About the role
Baya Systems's standard text
Baya Systems is inspired by the baya bird, also known as the weaver. Baya birds weave very unique and intricate hanging nests from different materials. The nests are robust and safe while being extremely lightweight and efficient.
Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems.
This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!
MICROARCHITECT AND RTL DESIGN ENGINEER
SANTA CLARA, CA
About the role:
We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities:
Design and develop microarchitectures for a set of highly configurable IPs
Microarchitecture and RTL coding ensuring optimal performance, power, area
Collaborate with software teams to define configuration requirements, verification collaterals, etc.
Work with verification teams on assertions, test plans, debug, coverage, etc.
Qualifications and Preferred Skills:
BS, MS in Electrical Engineering, Computer Engineering or Computer Science
8+ years and current hands-on experience in microarchitecture and RTL development
Proficiency in Verilog, System Verilog
Familiarity with industry-standard EDA tools and methodologies
Experience with large high-speed, pipelined, stateful designs, and low power designs
In-depth understanding of on-chip interconnects and NoC's
Experience within Arm ACE/CHI or similar coherency protocols
Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's
Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
Experience with modern programming languages like Python is a plus
Excellent problem-solving skills and attention to detail
Strong communication and collaboration skills
Compensation:
- Salary commensurate with experience
- Performance incentives
- Comprehensive medical, dental, and vision benefits
- 401(k) retirement plan
- Equity
What this role asks for
Standard for software engineering roles
Python
Common in software engineering postings at any company.
59% of this description is written for the role. The rest is Baya Systems's standard text, folded away below.
Compared with Baya Systems's other open jobs.
The team: Hardware
This role is one of 9 open in Hardware.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (8 of 9), Verilog (8 of 9)
OTHER ROLES ON THIS TEAM
- Manager/Director of Hardware Engineering posted Jul 2
- Hardware Verification Engineer posted Mar 25
- SOC-IP Architect posted Nov 7
- Microarchitect and RTL Design Engineer posted Jul 27
- Hardware Verification Engineer posted Jul 26
- Microarchitect and RTL Design Engineer posted Feb 14
- Hardware Verification Engineer posted Feb 14
- Hardware Verification Engineer posted Feb 13
From the team and dates on Baya Systems's own job board.
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