Physical Design SiP Architect
- Salary
- Not stated
- Level
- Lead
- Work type
- Not stated
- Visa
- Not stated
Open. First seen 7 October 2026.
The team: Semiconductor Engineering
This role is one of 11 open in Semiconductor Engineering. 11 were posted in the last 30 days.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Perl (7 of 11), Python (7 of 11), Verilog (2 of 11)
OTHER ROLES ON THIS TEAM
- DFT Architect (Physical Design & Chiplet) posted Sep 27
- Senior EDA / CAD Engineer posted Sep 27
- Senior RTL Design Engineer posted Sep 27
- SoC System Architect posted Sep 27
- Physical Design Architect posted Sep 27
- Lead STA Engineer posted Sep 26
- Senior Physical Design Engineer (Floorplan & PnR) posted Sep 26
- Senior Physical Design Engineer (Synthesis, SDC & STA) posted Sep 26
- VLSI Functional Safety Hardware Architect posted Sep 26
- Senior DFT Engineer posted Sep 26
From the team and dates on Envision Employment Solutions's own job board.
About the role
Envision Employment Solutions is currently looking for a Physical Design SiP Architect for one of our partners, an IT Services and IT Consulting company.
THE ROLE
As chiplets and system in package designs take over, the architecture no longer stops at the die edge. You'll define the physical architecture of SiP solutions, bringing dies, packaging, power, thermal and signal integrity together into one design that works as a system.
WHAT YOU'LL DO
- Define and document the physical architecture for system in package and chiplet based designs
- Lead architecture decisions on partitioning, die to die interfaces and package integration
- Drive power analysis, power integrity, thermal analysis and EMI considerations at package and system level
- Guide place and route and physical implementation strategy across dies
- Use system modelling (such as SystemC) to evaluate architecture options, including RISC based subsystems
- Write and own architecture definition documents
- Work across design, packaging and system teams to close on performance, power and cost
WHAT WE'RE LOOKING FOR
- 10+ years of experience in physical design and/or SoC architecture
- Hands on experience with SiP, chiplet or advanced packaging projects
- Strong understanding of power integrity, thermal analysis and EMI
- Solid place and route and physical design background
- Experience with SystemC modelling and RISC based architectures
- Strong architecture documentation skills
- Ability to lead technical decisions across multiple teams
YOU'LL THRIVE HERE IF YOU
- You think about the whole package, not just the die
- You enjoy weighing power, thermal and signal trade offs together
- You write architecture documents that people actually follow
- You're excited about where chiplet technology is heading
- You can bring design and packaging teams to one decision
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