CPU Physical Design Timing Engineer (Austin, TX)

The team: CPU Engineering

This role is one of 28 open in CPU Engineering. 18 were posted in the last 30 days.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Python (18 of 28), Perl (11 of 28), Verilog (9 of 28), VHDL (7 of 28), C++ (6 of 28), C (5 of 28), Embedded Systems (5 of 28)

OTHER ROLES ON THIS TEAM

• Principal CPU PPA Pathfinding Engineer posted Oct 13
• CPU Verification Engineer (Multiple Locations) posted Oct 13
• RTL Verification Engineer - Haifa posted Oct 13
• CPU Architect and Design - MMU & Security - Hod HaSharon posted Oct 12
• CPU Micro-architect/RTL Designer (Multiple Locations), Italy posted Oct 8
• CPU Verification Engineer posted Oct 8
• DV CAD Engineer posted Oct 7
• CPU SRAM Design Engineer posted Oct 7
• CPU Post-Silicon Performance Engineer posted Oct 7
• CPU Physical Design CAD Engineer (Sr Staff) posted Oct 6
• CPU Server Physical Design Methodology, Infrastructure and Automation Engineer posted Oct 6
• Software Engineer — RISC-V Random Test Generator posted Oct 2
• Senior Software Engineer — RISC-V Instruction Set Simulator (Simulator Engineer) posted Oct 2
• CPU Verification Engineer (RISC-V) posted Oct 2
• CPU Micro-Architecture and RTL Design Engineer (RISC-V) posted Oct 2
• CPU STA CAD Engineer posted Oct 2
• CPU SRAM Design Engineer - Sr Staff / Principal posted Oct 2
• CPU Server Physical Design Engineer, Santa Clara posted Oct 1
• CPU RTL/AI Micro-Architect - AI Development posted Sep 18
• CPU Micro-architect/RTL Designer posted Sep 18
• CPU Synthesis CAD Engineer posted Sep 17
• CPU Integration CAD Engineer posted Sep 17
• CPU Post-Silicon Validation Engineer - Multiple Levels posted Sep 17
• CPU Physical Design Engineer posted Sep 17
• Server Product Architect (RISC-V) – Sr. Director posted Sep 17
• RISCV CPU System RTL Engineer posted Sep 17
• CPU Integration & 3DIC CAD Engineer posted Sep 17

From the team and dates on Qualcomm's own job board.