Senior Systems Verification Engineer - Qualcomm - Sophia or Guyancourt, France
Bainbridge, Alpes-de-Haute-Provence, France
- Level
- Senior
- Work type
- On-site · Bainbridge
Not stated in the posting: salary, visa.
Open. First seen 27 October 2026.
About the role
Company: Qualcomm France S.A.R.L. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm Interconnect Technology (QITC) has been breaking ground in interconnect design for 15 years and continues to innovate and deliver technology in line…
What this role asks for
Particular to this role
FPGA · Verilog
Rare in Qualcomm's other 299 open postings.
In most of Qualcomm's ads
Python
Named in most of its open postings, whatever the role.
Compared with Qualcomm's other open jobs.
The team: ASICS Engineering HIRES STEADILY
This role is one of 128 open in ASICS Engineering. 64 were posted in the last 30 days and the oldest in December: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (69 of 128), Verilog (47 of 128), Perl (40 of 128), C (35 of 128), C++ (34 of 128), Embedded Systems (26 of 128), FPGA (17 of 128)
OTHER ROLES ON THIS TEAM
- Low Power Design/Methodology Engineer posted Oct 26
- SoC Power Design Engineer posted Oct 20
- (Sr) Staff SOC Architect - AI Accelerators (Multiple Locations) posted Oct 20
- Principal SOC Architect, AI Accelerators (Multiple Locations posted Oct 20
- Physical Design Engineer posted Oct 19
- ASICS Design Verification Engineer-Senior posted Oct 19
- SOC Limits Management Architect posted Oct 19
- ASICS Design Engineer, Senior Staff to Principal Level posted Oct 19
- Senior Staff Engineer - Microcontroller Sub-System Design posted Oct 14
- Video IP Design Verification Engineer posted Oct 14
- Principal Advanced Node Technology Yield & Diagnostics Engineer posted Oct 14
- Microcontroller Sub-System Design Engineer/ Staff Engineer posted Oct 14
- SOC Design Engineer posted Oct 13
- AI System Architect (NPU / GPU / Interconnect) posted Oct 13
- Design Verification Engineer — Memory Subsystem (Vancouver) posted Oct 13
- Senior SoC Debug Engineer posted Oct 13
- Senior Systems Design Engineer - Qualcomm - Sophia or Guyancourt - France posted Oct 13
- Design Engineer, Senior Staff/Manager posted Oct 13
- ASIC Modelling Engineer, Senior - Cork, Ireland posted Oct 12
- Lead Engineer - Pre/Post Si validation posted Oct 9
- DFT Engineer posted Oct 9
- SoC Sr Validation Engineer - Power Management posted Oct 9
- Tech IP Library Characterization Engineer posted Oct 8
- Physical Design Engineer, Sr. Staff posted Oct 8
- Staff Emulation Build Quality, Performance & Debug Engineer posted Oct 8
- Emulation Performance Methodology & Debug Engineer posted Oct 8
- Senior Emulation Performance Methodology & Debug Engineer posted Oct 8
- ASICS Design Verification Engineer (Vancouver, Markham OR Remote) posted Oct 8
- Video Design Verification - Sr Engineer posted Oct 8
- Next Gen, High-Speed, Memory and Cache Controller Design Engineer posted Oct 7
- Firmware Engineer, Edge AI Silicon Validation (Embedded C) posted Oct 7
- Front-End Implementation Engineer (Staff) (Timing & Synthesis)- Cork, Ireland posted Oct 7
- Memory Designer posted Oct 7
- ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham posted Oct 7
- Design Engineer - Hod Hasharon posted Oct 7
- SOC Design Verification Engineer posted Oct 7
- Director , Engineering (GPU Physical Design) posted Oct 7
- Hardware Verification, Engineer at Qualcomm Interconnect Technology Center (QITC) - France posted Oct 7
- Next-Gen System Cache ASIC Digital Design Engineer posted Oct 7
- EDA/CAD Software Engineer, Staff posted Oct 7
- DDRSS Systems Engineer posted Oct 7
- Memory Circuit Design Engineer posted Oct 7
- BEOL Process Integration Engineer, up to Sr. Staff posted Oct 6
- SOC Design Verification Engineer posted Oct 6
- SOC Debug Engineer posted Oct 6
- PMIC Design Verification Lead (Sr Staff Engineer) posted Oct 6
- Silicon Validation Senior Engineer posted Oct 6
- High-Bandwidth Memory (HBM) System Validation Lead (AI Accelerator Platform) posted Oct 6
- SOC Design Verification Staff Engineer posted Oct 5
- Camera Frontend Implementation Engineer posted Oct 5
- Physical Design (Multiple levels) posted Oct 2
- DFT-Staff Engineer posted Oct 2
- Architecture/System Validation Engineer posted Oct 2
- Systems Engineer (ML and DSP) - Cork, Ireland posted Oct 2
- SOC Design Verification Engineer posted Oct 2
- Physical Design Engineer posted Oct 2
- VLSI Frontend CAD Applications Engineer posted Oct 2
- Foundry Engineer for Advanced Technology (Device/Process/ Product) posted Oct 2
- Staff Analog IC Design Engineer (ADC) posted Oct 1
- Staff RF Hardware Engineer - Device Technology posted Oct 1
- Physical Design Engineer, Staff - Hod Hasharon posted Oct 1
- Design Verification Engineer - NPU- Engineer to Sr. Staff Engineer posted Oct 1
- SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team posted Oct 1
- Analog / Mixed-Signal IP DDR Design Senior Engineer - Cork, Ireland posted Sep 24
- Physical Design Engineer, Staff posted Sep 24
- Senior Staff Hardware Engineer - Hod Hasharon posted Sep 24
- SOC Power Architect posted Sep 23
- Microprocessor Silicon Validation and Optimization Engineer-Staff posted Sep 17
- Senior Director SoC Architecture - AI Accelerators (Multiple Locations) posted Sep 17
- Principal Ethernet Scale-Out Architect, AI Data Center posted Sep 17
- FPGA Firmware Engineer / FPGA Design Engineer posted Sep 17
- Physical Design Engineer- senior posted Sep 17
- CAD Engineer on ML/AI for Design Verification posted Sep 17
- VLSI Design Engineer for Server / Data Center Products posted Sep 17
- RTL Feasibility Engineer, AI/ML Processors posted Sep 17
- SOC Design Verification Engineer-Staff posted Sep 17
- Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels) posted Sep 17
- Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels) posted Sep 17
- 3D Memory Chip Architect and Design, Principal Engineer posted Sep 17
- FPGA Firmware Engineer / FPGA Design Engineer posted Sep 17
- Staff ASIC Verification Engineer, Low Power AI posted Sep 17
- SOC Design Engineer posted Sep 17
- Verification Hardware Engineer posted Sep 17
- ASICS Design Verification Engineer-Senior posted Sep 17
- Connectivity Project Engineer, Principal posted Sep 17
- Connectivity Project Engineer, Principal posted Sep 17
- ASIC DTCO, Timing and Technology Engineer posted Sep 17
- Sr. Staff/Principal PCIE Subsystem Architect posted Sep 17
- SOC Design Verification Engineer-Staff posted Sep 17
- SOC Design Verification Engineer posted Sep 17
- Staff Engineer, Physical Design/Implementation posted Sep 17
- Engineer posted Sep 17
- Digital Design Verification Engineer, Staff posted Sep 17
- Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer posted Sep 17
- Senior Design Verification Engineer- Haifa, Hod Hasharon, Ramat Gan posted Aug 4
- Video Codec Design Engineer, up to Staff posted Jul 31
- Software Engineer - Qualcomm - Guyancourt, France posted Jul 23
- NoC Verification Engineer - Qualcomm - Guyancourt, France posted Jul 23
- Microcontroller Sub-System Verification Engineer / Senior Engineer, - Cork, Ireland posted Jul 22
- Hardware Verification Senior/Staff/Senior Staff Engineer at Qualcomm Interconnect Technology Center (QITC) posted Jul 22
- Senior HW IP designer - Qualcomm - Guyancourt, France posted Jul 22
- Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France posted Jul 21
- Video Codec Digital Circuit Design Engineer posted Jul 21
- Architecture Engineer, Senior Staff - Hod HaSharon posted Jul 20
- SOC Design Verification Engineer– Pre-Si/Post-Si Verification posted Jul 20
- SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification posted Jul 20
- MBIST Diagnostics Engineer, up to Sr. Staff posted Jul 19
- Standard Cell Layout Engineer posted Jul 16
- Yield Diagnostics Engineer, up to staff posted Jul 16
- CPU Design Verification Engineer, Staff/ Sr Staff (RISC V) - Cork, Ireland posted Jul 13
- 3DIC Yield Analytics & Diagnostics Engineer, Staff posted Jul 10
- Advanced Node Process and Yield Diagnostics Engineer, Staff posted Jul 10
- SoC Design and Integration Engineer posted Jul 8
- Validation Engineer posted Jul 6
- CPU Microarchitect/RTL design Engineer, Senior/Staff - Cork, Ireland posted Jun 5
- HW Security Design Engineer posted May 21
- System Validation Engineer, Senior posted May 21
- CPU Physical Design Engineer - Cork, Ireland posted May 20
- IP Library Circuit Design Engineer posted May 20
- Sr QA Compiler posted May 7
- STA Design Engineer - Static Timing Analysis - Cork, Ireland posted May 6
- DRAM Circuit Designer, up to Staff posted Apr 13
- Staff Mixed Signal IC Design Engineer posted Apr 9
- High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei) posted Mar 20
- CPU RTL Design Engineer posted Mar 17
- CPU Design Verification Engineer - Cork, Ireland posted Jan 27
- DRAM PHY Designer, up to Staff posted Dec 30
From the team and dates on Qualcomm's own job board.
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