d-Matrix

Senior Staff Hardware Qualification Engineer

Santa Clara
Salary
$175K - $265K
Level
Staff
Work type
Hybrid · Santa Clara

Not stated in the posting: visa.

Open. First seen 6 November 2026.

Apply on the company's site →

About the role

d-Matrix's standard text

Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.

Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.

Role Overview

As a Senior Staff Hardware Qualification Engineer, you will be the final gatekeeper of quality and reliability for our next-generation AI compute platforms. This is a high-impact, technical leadership role responsible for defining the qualification strategies that ensure our hardware—from ASIC substrates to Rack scale systems — can withstand the rigorous demands of 24/7 data center environments. You will bridge the gap between design and mass production, ensuring that "cutting edge" doesn't mean "fragile."

Key Responsibilities

  • Qualification Strategy: Define and execute comprehensive HW qualification plans (EVT/DVT/PVT) for complex AI accelerator systems, including PCIe cards OAM modules and chassis systems.
  • Stress & Reliability Testing: Lead the implementation of HALT/HASS, thermal cycling, humidity, and vibration testing to identify marginalities in high-power ASIC designs.
  • Signal & Power Integrity Validation: Provide senior-level oversight for the validation of high-speed SerDes (112G/224G/PCIe), LPDDR, CoWOS designs, and complex PDN (Power Delivery Network) transients.
  • Failure Analysis (FA): Drive root-cause analysis for complex system-level failures, utilizing tools like X-ray, CT scan, and SEM/EDX to distinguish between design flaws, manufacturing defects, and material fatigue.
  • Interconnect Reliability: Specifically oversee the qualification of high-bandwidth interconnects (NVLink/UALink equivalents) and PCIe Gen5/6 link stability.
  • Cross-Functional Influence: Work directly with Design, Thermal, and Firmware teams to implement hardware fixes based on qualification data.
  • Vendor Management: Partner with CMs (Contract Manufacturers) and JDMs to align on test methodologies and production outgoing quality limits (OQL).

What you will bring

  • Education: BS/MS in Electrical Engineering, Mechanical Engineering, or Reliability Engineering.
  • Experience: 12+ years in hardware qualification or reliability, specifically with high-performance computing (HPC), servers, or networking hardware.
  • Technical Depth: Mastery of JEDEC, IPC, and Telcordia standards for hardware reliability.
  • Diagnostic Skills: Expert-level experience with high-speed oscilloscopes, logic analyzers, and environmental chambers.
  • Statistical Proficiency: Strong command of statistical methods (Weibull analysis, DOE, and JMP/Minitab) to predict product life cycles and failure rates.

Preferred Qualifications

  • Experience qualifying Air and Liquid Cooling components (CDUs, cold plates, leak detection) for high-TDP AI systems.
  • Background in ASIC/Package-level reliability, including electromigration and Thermal Stress Analysis.
  • Familiarity with Python or LabVIEW for automating complex test sequences.
d-Matrix's standard text

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication, and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.

What this role asks for

Particular to this role

LabVIEW

Rare in d-Matrix's other 65 open postings.

Standard for embedded / hardware roles

Embedded Systems

Common in embedded / hardware postings at any company.

In most of d-Matrix's ads

Python

Named in most of its open postings, whatever the role.

56% of this description is written for the role. The rest is d-Matrix's standard text, folded away below.

Compared with d-Matrix's other open jobs.

The team: Systems Engineering

This role is one of 6 open in Systems Engineering.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Embedded Systems (4 of 6), PCB Design (4 of 6), Python (4 of 6), LabVIEW (2 of 6)

OTHER ROLES ON THIS TEAM

From the team and dates on d-Matrix's own job board.

Other openings for this role

2 open postings for this role in Santa Clara, first posted 2 October 2026. The company is likely hiring for more than one position. None has been taken down and posted again.

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SKILLSEmbedded Systems 7,689
PLACESSanta Clara 944United States 77,474
COMPANYJobs at d-Matrix 66

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