d-Matrix

Sr. Staff PCB Design Engineer

Santa Clara
Salary
$175K - $265K
Level
Staff
Work type
Hybrid · Santa Clara

Not stated in the posting: visa.

Open. First seen 6 November 2026.

Apply on the company's site →

About the role

d-Matrix's standard text

Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.

Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.

Role Overview

As Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss.

Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up.

What You Will Do

  • Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards
  • Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints
  • Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting
  • Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects
  • Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs
  • Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups
  • Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production

What You Will Bring

  • BS in Electrical/Electronic Engineering or equivalent practical experience
  • 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
  • Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching
  • Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines
  • Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design
  • Proven track record routing 112G SerDes and complex DDR5/HBM interfaces

Preferred Qualifications

  • Experience establishing a Library Management System and standardized footprint/padstack creation processes
  • Familiarity with PLM/PDM integration for managing layout releases and ECO workflows
  • Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs
d-Matrix's standard text

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication, and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.

What this role asks for

Particular to this role

PCB Design

Rare in d-Matrix's other 65 open postings.

In most of d-Matrix's ads

Python

Named in most of its open postings, whatever the role.

57% of this description is written for the role. The rest is d-Matrix's standard text, folded away below.

Compared with d-Matrix's other open jobs.

The team: Systems Engineering

This role is one of 6 open in Systems Engineering.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Embedded Systems (4 of 6), PCB Design (4 of 6), Python (4 of 6), LabVIEW (2 of 6)

OTHER ROLES ON THIS TEAM

From the team and dates on d-Matrix's own job board.

Other openings for this role

2 open postings for this role in Santa Clara, first posted 2 October 2026. The company is likely hiring for more than one position. None has been taken down and posted again.

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