Hardware Engineer, Design Verification

The Role

Hybrid: 3 days a week in the office, in Mountain View, New York or London.

As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs from architecture through tapeout, and help set the bar for the AI-assisted verification flows we are building for ourselves. You will own verification of complex IPs and subsystems, develop reusable verification infrastructure, and establish methodologies that enable efficient, scalable verification across our silicon programs.

You will also work closely with our architecture, RTL, and software teams to integrate AI-assisted tools into everyday verification workflows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.

What You Will Own

• ASIC Design Verification: Own end-to-end verification of Normal's internal ASICs, including verification planning, testbench development, assertions, functional coverage, regression, and coverage closure through tapeout.
• Verification Architecture & Methodology: Develop scalable SystemVerilog/UVM verification environments, reusable VIP, scoreboards, reference models, and verification methodologies across IP, subsystem, and SoC levels.
• AI-Native Verification Workflows: Develop and integrate AI-assisted verification workflows, including specification analysis, test planning, testbench generation, debugging, and coverage closure. Review AI-generated verification collateral and help define what good looks like, so the tools the team builds raise the bar rather than lower it.
• Verification Infrastructure & Tooling: Build and maintain regression infrastructure, CI/CD integration, coverage analysis, and EDA tool flows to support efficient and repeatable ASIC verification.
• Cross-Functional Collaboration: Work closely with architecture, RTL design, physical design, and software teams to identify verification requirements, resolve design ambiguities, and drive silicon quality.

What Makes You a Great Fit

• 5+ years of experience in digital design verification for complex ASICs, SoCs, or IPs
• Advanced proficiency in SystemVerilog, UVM, SystemVerilog Assertions (SVA), and constrained-random verification
• Proven experience in end-to-end verification, including verification planning, testbench architecture, stimulus generation, scoreboards, and functional coverage closure
• Strong understanding of industry-standard protocols such as AXI, APB, AHB, or other SoC interconnects
• Experience with EDA simulation, debugging, and coverage tools such as Cadence Xcelium, SimVision, vManager, Synopsys VCS, or Verdi
• Strong scripting and automation skills using Python, Tcl, or similar languages
• Experience developing reusable verification environments and debugging complex RTL and system-level issues
• Strong communication and collaboration skills, with the ability to work across hardware and software teams

Bonus Points

• Experience building verification infrastructure and methodologies from the ground up for a new ASIC program
• Hands-on experience using LLMs, AI coding assistants, or agentic tools for RTL design and verification
• Experience with formal verification, power-aware verification, or emulation
• Exposure to AI accelerators, memory subsystems, in-memory computing, or unconventional compute architectures