Design for Test (DFT) Engineer

About the Team

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About this Role

You'll make sure the chips we work on can be tested in manufacturing and in the field. You'll own DFT architecture and implementation on real silicon programs with leading semiconductor companies while helping Voltai's AI learn DFT methodology.

What You’ll Do

• Define DFT architecture for SoCs and IP, including scan, compression, MBIST, LBIST, and boundary scan.
• Insert and verify DFT logic, and generate ATPG patterns that meet coverage targets.
• Work with RTL, synthesis, and physical design teams to close DFT timing and area impact.
• Support silicon bring-up, pattern debug, and yield analysis with test and product engineering.
• Build automation for DFT flows and coverage reporting.
• Help define how AI can accelerate DFT insertion and pattern generation.

What We’re Looking For

• 5+ years of DFT experience on production tapeouts.
• Hands-on experience with Tessent, TestMAX, or Modus.
• Strong knowledge of scan, compression, ATPG, MBIST, and IEEE 1149.1/1687.
• Experience with DFT verification and gate-level simulation.
• Tcl and Python scripting.

Bonus Points

• Post-silicon test bring-up and ATE experience.
• Experience with 2.5D/3D or chiplet test strategies.
• Interest in AI-assisted design tools.