CAD & Flow Methodology Engineer

About the Team

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About this Role

You'll build the infrastructure that connects the whole chip design flow. You'll own design flows across frontend and backend while building the bridge between industry EDA tools and Voltai's AI systems.

What You’ll Do

• Build and maintain design flows spanning RTL, synthesis, STA, place and route, and signoff.
• Integrate commercial EDA tools with Voltai's AI agents and data pipelines.
• Build regression, tracking, and reporting infrastructure for design and verification.
• Manage EDA licenses, compute infrastructure, and job scheduling at scale.
• Partner with ML researchers to generate and curate large-scale design data.
• Support customer deployments in locked-down on-prem environments.

What We’re Looking For

• 5+ years of CAD, flow, or methodology experience at a semiconductor or EDA company.
• Hands-on experience with major Synopsys and Cadence tools.
• Strong Python and Tcl, plus solid software engineering practices.
• Experience with LSF, Slurm, or similar compute farm infrastructure.
• Understanding of the full RTL-to-GDSII flow.

Bonus Points

• Experience with cloud or Kubernetes-based EDA infrastructure.
• Experience with open-source EDA tools (Yosys, OpenROAD).
• Background in ML data pipelines.