Physical Design Engineer

About the Team

Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.

About this Role

You'll take designs from netlist to GDSII. You'll own floorplanning through closure on real silicon programs with leading semiconductor companies while helping Voltai's AI learn how expert physical designers make decisions.

What You’ll Do

• Own block-level and full-chip physical implementation: floorplanning, placement, clock tree synthesis, and routing.
• Drive timing, power, and congestion closure with synthesis and STA teams.
• Close physical verification (DRC/LVS) and power integrity (IR drop, EM) for signoff.
• Build and improve place-and-route flows and automation.
• Evaluate AI-generated floorplans and implementation decisions, and help define what good looks like.
• Work directly with customer teams on implementation challenges.

What We’re Looking For

• 5+ years of physical design experience with multiple production tapeouts.
• Deep experience with Innovus or Fusion Compiler/ICC2.
• Strong understanding of timing closure, clock tree synthesis, and power distribution networks.
• Experience at advanced nodes (7nm and below).
• Strong Tcl and Python scripting.

Bonus Points

• Full-chip integration or hierarchical design experience.
• Experience with high-speed or low-power designs.
• Interest in AI or machine learning applied to physical design.