Senior System Validation Engineer
- Salary
- Not stated
- Level
- Senior
- Work type
- Not stated
- Visa
- Not stated
Open. First seen 2 October 2026.
The team: ASIC Engineering HIRES STEADILY
This role is one of 50 open in ASIC Engineering. 11 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (33 of 50), Verilog (20 of 50), Embedded Systems (19 of 50), Perl (13 of 50), C (9 of 50), C++ (8 of 50), FPGA (5 of 50)
OTHER ROLES ON THIS TEAM
- Principal Digital Design Engineer posted Oct 5
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Digital Design Manager posted Sep 15
- Principal Digital Design Engineer posted Sep 14
- Manager Design Verification posted Sep 14
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Senior ATE Test Engineer posted Aug 31
- Manager, ATE Test Engineering posted Aug 28
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Physical Design Engineer, Methodology posted Jul 22
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- Soc Design Verification Director posted Jun 24
- Principal DFT Engineer posted Jun 8
- Staff DFT Engineer posted Jun 8
- Staff Physical Design Engineer - SoC EMIR Engineer posted Jun 7
- Physical Design Student posted Jun 2
- Staff/ Principal Design Verification Engineer posted Jun 1
- Senior Design Verification Engineer posted Jun 1
- Principal Physical Design Engineer, STA posted May 20
- Principal Product Engineer posted Apr 1
- Manager, Package Design Engineering posted Mar 26
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- Principal ATE Test Engineer posted Dec 19
- Technical Chief of Staff for ASIC Engineering posted Nov 20
- Principal Emulation Engineer posted Sep 9
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Senior System Validation Engineer
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ technologies with the company’s COSMOS software suite to enable scalable, high-performance AI infrastructure. Discover more at www.asteralabs.com.
Overview:
Astera Labs is seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.
Basic Qualifications:
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
6+ years of experience in post-silicon, system, hardware, or product validation.
Hands-on experience with SoC/silicon bring-up, functional validation, and system-level debug.
Experience developing and executing validation plans, test cases, and characterization experiments.
Strong Python scripting and test automation skills.
Strong hardware debugging, analytical, and problem-solving skills with the ability to work independently.
Experience debugging issues across hardware, firmware, and software.
Experience validating high-speed interfaces such as PCIe, Ethernet, SerDes, CXL, or DDR.
Hands-on experience working in a hardware or system validation laboratory.
Strong communication and cross-functional collaboration skills.
Preferred Qualifications:
Experience with PVT validation, silicon corner testing, characterization, qualification, and margin analysis.
Experience with server, storage, networking, or AI infrastructure products.
Familiarity with PCIe/CXL architecture and high-speed SerDes technologies.
Experience with oscilloscopes, BERTs, protocol analyzers, traffic generators, or similar lab equipment.
Working knowledge of Python, firmware, Linux, and system-level software debugging.
Experience developing automated validation and regression environments.
Familiarity with Git and software development practices.
Experience with pre-silicon validation, emulation, or hardware prototyping.
Experience with system performance, throughput, latency, power, and stability testing.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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