Soc Design Verification Director
- Salary
- Not stated
- Level
- Lead
- Work type
- Not stated
- Visa
- Not stated
Open. First seen 2 October 2026.
The team: ASIC Engineering HIRES STEADILY
This role is one of 50 open in ASIC Engineering. 11 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (33 of 50), Verilog (20 of 50), Embedded Systems (19 of 50), Perl (13 of 50), C (9 of 50), C++ (8 of 50), FPGA (5 of 50)
OTHER ROLES ON THIS TEAM
- Principal Digital Design Engineer posted Oct 5
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Senior System Validation Engineer posted Sep 16
- Digital Design Manager posted Sep 15
- Principal Digital Design Engineer posted Sep 14
- Manager Design Verification posted Sep 14
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Senior ATE Test Engineer posted Aug 31
- Manager, ATE Test Engineering posted Aug 28
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Physical Design Engineer, Methodology posted Jul 22
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- Principal DFT Engineer posted Jun 8
- Staff DFT Engineer posted Jun 8
- Staff Physical Design Engineer - SoC EMIR Engineer posted Jun 7
- Physical Design Student posted Jun 2
- Staff/ Principal Design Verification Engineer posted Jun 1
- Senior Design Verification Engineer posted Jun 1
- Principal Physical Design Engineer, STA posted May 20
- Principal Product Engineer posted Apr 1
- Manager, Package Design Engineering posted Mar 26
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- Principal ATE Test Engineer posted Dec 19
- Technical Chief of Staff for ASIC Engineering posted Nov 20
- Principal Emulation Engineer posted Sep 9
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
About the role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Title: Director of SoC Design Verification
Overview
We are seeking a seasoned Director of SoC Design Verification with 20+ years of experience to lead verification for our next-generation System-on-Chip products. This is a hands-on leadership role where you will define the SoC-level verification strategy, oversee execution across multiple IPs and subsystems, and ensure first-pass silicon success for complex designs in compute, networking, and storage domains.
Key Responsibilities
- Own and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments.
- Lead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration.
- Guide verification of complex SoC subsystems including HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols.
- Champion advanced methodologies (UVM, formal verification, emulation, AI-augmented flows) to accelerate coverage closure and improve efficiency.
- Collaborate closely with RTL design, architecture, firmware, and validation teams to debug, refine, and optimize SoC-level verification processes.
- Represent verification in executive reviews, customer engagements, and industry forums.
- Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges.
Qualifications
- Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
- 20+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
- Deep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems.
- Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
- Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.
Required Experience
- Hands-on expertise with SoC-level verification environments, including integration of multiple IPs, HSIO, and peripherals.
- Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
- Strong background in writing assertions, cover properties, and analyzing coverage data at both IP and SoC levels.
- Experience in developing scalable verification infrastructures to simplify and accelerate SoC-level deployments.
Preferred Experience
- Expertise in verifying complex SoC subsystems such as NoC-based interconnects, coherency fabrics, HSIO, and memory hierarchies.
- Experience with buffering, queuing, QoS, and system-level performance analysis.
- Familiarity with emulation, FPGA prototyping, and hybrid verification flows.
- Knowledge of AI-driven verification methodologies and workforce transformation strategies.
- Experience with AI/ML accelerators, networking, automotive, data center, or high-performance computing SoCs.
- Familiarity with low-power verification methodologies and power-aware verification.
Why Join Us?
- Opportunity to lead cutting-edge SoC development programs.
- Influence verification strategy across next-generation products.
- Build and grow a world-class verification organization.
- Work with highly talented engineering teams on innovative technologies.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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