IP Design Director
- Level
- Lead
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
Astera Labs's standard text
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description – IP Digital Design Manager
Position Overview
We are seeking an experienced and highly motivated Digital Design Manager to lead the micro-architecture, design, development, and delivery of IPs and Subsystems from for next-generation switch products. This role combines deep technical expertise with strong people leadership and program management skills.
The successful candidate will be responsible for managing a team of IP digital design engineers while driving the successful execution of complex IP development programs. The role requires close collaboration with Architecture, Verification, Physical Design, DFT, Firmware, Software, Product Engineering, and SoC Integration teams to ensure delivery of high-quality IPs that meet performance, power, area, quality, and schedule objectives.
This position offers the opportunity to influence product roadmaps, establish engineering best practices, and contribute to the development of industry-leading semiconductor solutions.
Key Roles & Responsibilities
Technology Background
- Deep understanding of complex networking protocols such as PCIE, UALink, Ethernet is a must
- Experience of working on latest generations of these protocols is highly desirable.
- Expertise of standard front-end design flows / tools / HDLs for digital design
Technical Leadership
- Lead the end-to-end development of digital Ips / Subsystems from architecture through silicon validation.
- Partner with architects and product teams to define IP requirements, features, performance targets, and scalability needs.
- Drive microarchitecture development and ensure alignment with overall SoC and product requirements.
- Review and approve architecture specifications, design documents, RTL implementations, and verification plans.
- Ensure IP designs achieve performance, power, area (PPA), reliability, and quality targets.
- Lead technical reviews and provide guidance on complex design challenges.
- Drive design trade-off decisions and risk mitigation strategies.
- Lead the post-silicon support once silicon is back in the lab. Prior experience of post-silicon work is highly desirable.
IP Development & Delivery
- Own the successful delivery of IP/Subsystem releases according to committed schedules and quality goals.
- Ensure all IP deliverables, including RTL, verification collateral, documentation, synthesis constraints, and integration guides, are completed and released on time.
- Drive IP reuse strategies to maximize engineering efficiency across multiple products and platforms.
- Establish standards for IP packaging, version control, configuration management, and release processes.
- Ensure compliance with internal design methodologies and industry best practices for all front-end flows such as Lint, CDC, Power Analysis, Timing Constraints.
- Work with cross-functional teams to ensure that requirements, dependencies from all stakeholders are met and incorporated into the deliverables
Team Leadership & People Management
- Build, lead, and mentor a high-performing IP design team.
- Set clear goals and expectations for team members.
- Conduct performance reviews, development planning, and regular coaching sessions.
- Identify skill gaps and implement training and development initiatives.
- Participate in workforce planning, recruiting, interviewing, hiring, and onboarding activities.
- Foster an inclusive, collaborative, and innovation-driven culture.
- Promote technical excellence and continuous learning within the organization.
Required Qualifications
Education
- Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field.
- Master's degree preferred.
Experience
- 15+ years of experience in semiconductor design and development.
- 5+ years of experience managing engineering teams and complex IP development programs.
- Proven track record of successfully delivering multiple IPs into production silicon.
- Experience managing cross-functional engineering programs across geographically distributed teams.
- Experience delivering IPs for AI, networking, datacenter, automotive, mobile, or high-performance computing products.
- Experience leading global engineering teams.
- Experience managing multiple concurrent IP development programs.
- Familiarity with safety-critical and security-focused design methodologies.
- Experience driving IP reuse strategies across multiple product generations.
Astera Labs's standard text
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
What this role asks for
81% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.
Compared with Astera Labs's other open jobs.
The team: ASIC Engineering HIRES STEADILY
This role is one of 51 open in ASIC Engineering. 16 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (32 of 51), Embedded Systems (24 of 51), Verilog (20 of 51), Perl (14 of 51), C (8 of 51), C++ (7 of 51), FPGA (4 of 51)
OTHER ROLES ON THIS TEAM
- Principal Verification Engineer posted Oct 26
- Physical Design Team Lead posted Oct 25
- Physical Design Engineering Director posted Oct 24
- Principal Physical Design Engineer posted Oct 22
- Firmware Engineer posted Oct 20
- Principal Digital Design Engineer posted Oct 14
- Principal Physical Design Engineer posted Oct 12
- Principal Physical Design CAD Engineer posted Oct 11
- Principal Digital Design Engineer posted Oct 5
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Senior System Validation Engineer posted Sep 16
- Digital Design Manager posted Sep 15
- Principal Digital Design Engineer posted Sep 14
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Senior ATE Test Engineer posted Aug 31
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- SoC Design Director posted Jun 29
- Soc Design Verification Director posted Jun 24
- Principal Architect posted Jun 9
- Physical Design Student posted Jun 2
- Product Technical Chip Lead, Senior Director posted Apr 9
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- STA Physical Design Engineer, Senior Principal posted Feb 24
- Expert IC Package Design Lead posted Feb 22
- Technical Chief of Staff for ASIC Engineering posted Nov 20
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
Similar jobs
- Principal Verification Engineer at Astera Labs
Also at this company - Physical Design Team Lead at Astera Labs
Also at this company - Physical Design Engineering Director at Astera Labs
Also at this company - Principal Sourcing Manager – Silicon Technologies at Astera Labs
Also at this company - Principal Physical Design Engineer at Astera Labs
Also at this company - Senior Principal Engineer- Field Applications at Astera Labs
Also at this company
More jobs like this
Is this your posting? Email info@careerholo.com to have it removed.