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Astera Labs

Senior SoC Verification/Validation Engineer

San Jose, CA
Salary
$165,000
Level
Senior
Work type
Not stated
Visa
Not stated

Open. First seen 2 October 2026.

Apply on job-boards.greenhouse.io →

The team: ASIC Engineering HIRES STEADILY

This role is one of 50 open in ASIC Engineering. 11 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Python (33 of 50), Verilog (20 of 50), Embedded Systems (19 of 50), Perl (13 of 50), C (9 of 50), C++ (8 of 50), FPGA (5 of 50)

OTHER ROLES ON THIS TEAM

From the team and dates on Astera Labs's own job board.

About the role

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for Senior SoC Verification/Validation Engineer who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out.

Basic Responsibilities

  • Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures
  • Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality
  • Collaborate closely with Architecture, Design, Verification, and SW/FW teams to define and execute functional/performance validation plans
  • Develop C/C++ FW and tests to validate and execute all test plan items
  • Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform

Required Qualification

  • BS/MS in Electrical Engineering, Computer Engineering or related field.
  • 5+ years of hands-on experience in pre-silicon verification/validation.
  • Strong hands-on experience in running and debugging SOC simulation.
  • Protocol knowledge in high-speed protocols such as PCIe, UALink and/or Ethernet is essential
  • Proficiency in programming and scripting languages (System Verilog, C/C++, Python)
  • Strong debugging and analytical skills
  • Excellent communication skills and ability to work independently with minimal supervision.
  • Currently based locally or open to relocation.

Preferred Experience:

  • Bring up and validation experience using the industry standard emulation platforms (Palladium or Zebu)
  • Hands-on experience in running and debugging SOC simulation and emulation platforms.

The base salary range is $165,000 USD - $195,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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